1. Field of the Invention
The present invention relates to an improvement of a liquid crystal display device and a data line drive circuit for driving the data lines of the same.
2. Description of the Related Art
FIG. 8 is a circuit diagram of an example of the configuration of a liquid crystal display device using a thin film transistor (TFT) drive system.
As shown in FIG. 8, this liquid crystal display device 1 is constituted by a thin film transistor switch matrix portion 2. a gate line drive circuit 3, a data line drive circuit 4, a timing control circuit 5, a gate circuit 6, and a data line control circuit 7.
In the thin film transistor switch matrix portion 2, thin film transistor switches 21 are arranged in the form of a matrix.
Each thin film transistor switch 21 is constituted by thin film transistor 21a, a liquid crystal element 21b, and a counter electrode 21c. Further, the drain of each thin film transistor 21a is connected to a pixel electrode.
The gate electrodes of the thin film transistors 21a of the thin film transistor switches 21 arranged in the same row are connected to the same gate lines GL1 to GLM, while source electrodes of the thin film transistors 21a of the thin film transistor switches 21 connected in the same column are connected to the same data lines DL1 to DLN.
The gate line drive circuit 3 sequentially supplies a drive voltage to the gate lines GL1 to GLM.
The data line drive circuit 4 has n (for example n=6) number of sample-and-hold circuits, allocates the input video signal VIN to a plurality of n number of outputs at a timing controlled by a control signal CTL51 of the timing control circuit 5, and outputs n number of signals D1 to D1n at the same time at a timing where all outputs are ready.
FIG. 9 is a block diagram of an example of the configuration of the data line drive circuit 4.
As shown in FIG. 9, the data line drive circuit 4 is constituted by n number of sample-and-hold circuits 41-1 to 41-n connected in parallel to an input terminal TIN of the video signal VIN and drive circuits 42-1 to 42-n connected between outputs of the sample-and-hold circuits 41-1 to 41-n and output terminals TOUT1 to TOUTn, respectively.
In the data line drive circuit 4 of FIG. 9, switching control of a sampling time and a holding time of the sample-and-hold circuits 41-1 to 41-n is carried out based on the control signal CTL51 from the timing control circuit 5, input video signals VIN are allocated to a plurality of n number of outputs, and n number of signals D1 to D1n are output from the output terminals TOU1 to TOUTn at the same time via the drive circuits 42-1 to 42-n at a timing when all outputs are ready.
The n number of output terminals TOUT1 to TOUTn of the data line drive circuit 4 are connected in parallel to N number of data lines DL1 to DLN in units of n numbers via the thin film transistors 61-1 to 61-N (N&gt;n) constituting the gate circuit 6.
The gate electrodes of the thin film transistor 61-1 to 61-N of the gate circuit 6 are connected to output lines of control signals CTL71 to CTL7x of the data line control circuit 7 in units of n numbers, and the thin film transistor 61-1 to 61-N are sequentially controlled to turn on in units of n numbers.
The reason why use was made of the method of driving the data lines DL in units of n numbers instead of driving the same one by one in the data line drive circuit 4 explained above was that the time allotted per dot has become shorter along with improvement of the precision of the liquid crystal display device and it has become difficult to charge (or discharge) a wiring capacitance load attached to a data line (indicated by CL in FIG. 8) and give a stable voltage within that time.
Namely, this is because if outputs of a plurality of dots (for example, n number) can be output at the same time, n times the time can be secured, so it becomes easy to give a stable voltage.
When this method is used, however, since the signals allocated to each n number of dots pass through different sample-and-hold circuits and drive circuits, an offset difference is liable to be produced among the outputs.
As the cause of the offset difference, the offset due to a droop of the sample and hold and an offset due to the driver can be considered in terms of the circuit.
This offset will be further considered by referring to FIGS. 10A and 10B and FIG. 11.
For example, if the data line drive circuit is realized by one integrated circuit (IC) as in FIG. 10A, there is a possibility of occurrence of a difference of about +50 mV due to the difference in characteristics among the elements inside the integrated circuit.
Further, if it is realized in a plurality of integrated circuits as shown in FIG. 10B, there is a possibility that a difference of about +100 mV due to the difference in characteristics among integrated circuits will be further added to this.
FIGS. 11A to 11D are views of an example of input and output of the video signal.
As shown in FIG. 11A, when assuming that the input video signal is a flat signal, ideally, as shown in FIG. 11B, the output signal must also be flat.
In actuality, however, as in FIG. 10A, the output of one IC becomes as shown in FIG. 11C, and as in FIG. 10B, the output of the plurality of integrated circuits becomes as shown in FIG. 11D (note, in FIG. 11D, m=2 in FIG. 10B).
Due to this difference in offsets among outputs, when the method of driving the data lines DL in units of n numbers instead of driving them one by one is adopted in the data line drive circuit of the related art, if this data line drive circuit is used in a high gradation liquid crystal display device, a repeating pattern of vertical stripes is generated on the screen, therefore there was the disadvantage of degradation of the image quality.